spam

[David Lindon]

So what do you want me to do?

 

[Iowa]

dont drag dragonjames,highlander,bennett or anybody else on my side into it.if you want,i will take full responsibility for the war.

can we stop arguing?

 

[David Lindon]

OK, all made up with the war finished now?

 

[Dragonjames2]

Well Kieth al i can say is that Dave likes you so I have nothing against you. I am very friendly. I am going to be amnn accountaant Maelmored

 

[Dragonjames2]

Oh and another thing Keith, Your analysis that i am hiding from myself is a very good analysis. Although it is not true, it is an A-Grade answer at AS Level, so keep it up. I will now take back that you are uneducated, it looks like you are educated. I am impressed

 

[job7evans]

front side bus settings

This post is a response to what serpentracer said about pentium 4s and celerons: "the standard Celerons today run at 400mhz. p4 533 mhz, p4 ht 800mhz"

yes and no, here is a chart to help u all understand Front Side Bus and Data Transfer rates of diff. processors:

applying to the quote above this chart is correct:

FSB = Front Side Bus
DTR = Data Transfer rate

Celeron (socket 423/478): FSB = 100Mhz
DTR = 400Mhz (100Mhz x 4)

P4 (socket 423): FSB = 100Mhz
DTR = 400Mhz (100Mhz x 4)

P4 (socket 478): FSB = 133Mhz versions and 200Mhz versions
DTR = 533Mhz versions and 800Mhz versions

I hope that that chart clarified certain head aches. The chip runs at the front side bus speed, and the data is processed at the DTR rate, do not ask me why its this way because i don't exactly know, but the FSB is the rate at which data is moved from all components in the computer to one another and to the processor (CPU). ttyl...

 

[job7evans]

FSB and DTR settings

This post is a response to what serpentracer said about pentium 4s and celerons: "the standard Celerons today run at 400mhz. p4 533 mhz, p4 ht 800mhz"

yes and no, here is a chart to help u all understand Front Side Bus and Data Transfer rates of diff. processors:

applying to the quote above this chart is correct:

FSB = Front Side Bus
DTR = Data Transfer rate

Celeron (socket 423/478): FSB = 100Mhz
DTR = 400Mhz (100Mhz x 4)

P4 (socket 423): FSB = 100Mhz
DTR = 400Mhz (100Mhz x 4)

P4 (socket 478): FSB = 133Mhz versions and 200Mhz versions
DTR = 533Mhz versions and 800Mhz versions

I hope that that chart clarified certain head aches. The chip runs at the front side bus speed, and the data is processed at the DTR rate, do not ask me why its this way because i don't exactly know, but the FSB is the rate at which data is moved from all components in the computer to one another and to the processor (CPU). ttyl...

 

[135791]

man this is old did you read the dates in which it was posted

 

[David Lindon]

Too old. Time to let it go.