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Old 08-30-2005, 05:04 AM   #1
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Join Date: Aug 2005
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Question computer architecture problem

Hi,

This is the scenario of my problem:

The instruction set for your architecture has 44-bit addresses, with
each
addressable item being a byte. You elect to design a four-way set
associative
cache with each of the four lines in a set containing 64 bytes. Assume
that
you have 256 sets in the cache.

a) Show how the 44-bit physical address is treated in performing a
cache
reference.

b) Consider the following sequence of addresses in hexadecimal.

0E1B01AA050 0E1B01AA073 0E1B2FE3057 0E1B4FFD85F 0E1B01AA04E

In your cache, what will the tags be in the set(s) that contain
these references at the end of the sequence? Assume some initial
state. Show the initial and final states.

c) The cache is four-way set associative. What is the fewest number
of bits required to keep track of which line to replace when
replacement is
LRU? Show your solution.

d) We can construct a cache with the identical number of data bytes
by doubling the line size and by reducing set associativity to 2. How
does this change the cost of the cache as measured in total bits?


thanks!

hoping for help....
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