Re: AMD ZEN'S HYPERQUIZ! (Week3)
VOTING IS OVER!!! AND THE CORRECT ANSWER IS............!!!
L1 A= Instruction Sets, L1 B= Data Bank Cache
Now for a little explanation as to why this correct (just for you my dear Lord K..
AMD Processors rely on their FULLY INTEGRATED instruction commands from SSE, SSE2, MMX, 3DMax!, and 3DMax! + to be readily available. Therefore, they are but into the first 64KB block of L1 Cache to be accessed at enormous speeds by the AMD processor. The second cache (which is where many people got confused) is for processor command data storage. The L1 Cache acts as the processors psyche, allowing it to see into the future by up to 10 million commands on AMD and 1.2Million on Pentium4's (30 million on the Penitum Ms!) The L1 Cache is purely internal. If you didn't understand my hint, that basically means that the ENTIRE L1 cache is inside the the chip, next to the die of the processor. That means that is does NOT associate with ANY external force in the PC, but rather only the string threads that the processor has to push out. In fact, the L1 Cache allows for the GFlops to be pushed otu correctly from the center die core of the CPU, and in effect allows for a pathway for the binary string threads to flow freely from the L1 Cache to the L2 Cache or directly to the Memory.