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Old 02-19-2005, 12:15 PM   #81
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Default Re: AMD ZEN'S HYPERQUIZ! (Week3)

Quote:
Originally Posted by Lord Kalthorn
Got to be Data Instructions - cause MSN Search said so.
MSN SUX's Google Pwns all man
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Old 02-19-2005, 01:01 PM   #82
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Default Re: AMD ZEN'S HYPERQUIZ! (Week3)

VOTING IS OVER!!! AND THE CORRECT ANSWER IS............!!!

L1 A= Instruction Sets, L1 B= Data Bank Cache

Now for a little explanation as to why this correct (just for you my dear Lord K..

AMD Processors rely on their FULLY INTEGRATED instruction commands from SSE, SSE2, MMX, 3DMax!, and 3DMax! + to be readily available. Therefore, they are but into the first 64KB block of L1 Cache to be accessed at enormous speeds by the AMD processor. The second cache (which is where many people got confused) is for processor command data storage. The L1 Cache acts as the processors psyche, allowing it to see into the future by up to 10 million commands on AMD and 1.2Million on Pentium4's (30 million on the Penitum Ms!) The L1 Cache is purely internal. If you didn't understand my hint, that basically means that the ENTIRE L1 cache is inside the the chip, next to the die of the processor. That means that is does NOT associate with ANY external force in the PC, but rather only the string threads that the processor has to push out. In fact, the L1 Cache allows for the GFlops to be pushed otu correctly from the center die core of the CPU, and in effect allows for a pathway for the binary string threads to flow freely from the L1 Cache to the L2 Cache or directly to the Memory.
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Old 02-19-2005, 01:29 PM   #83
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The difference between Prime Instructions and Instruction Sets, and RAM Data Caching and Data Bank Cache is?
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Old 02-19-2005, 01:33 PM   #84
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Default Re: AMD ZEN'S HYPERQUIZ! (Week3) VOTING OVER!!!!

ERg.... Did I just not explain that....

Instruction sets= MMX, SSE, SSE2, 3DMax!, etc.

Prime Instructions= Binary Threading commands using Prime Number sets to encode Binary.

RAM Data Caching= L2 Caches job, it stores information is strings that memory needs readily available and can send the to CPU at many different intervals.

Data Bank Cache= Processor OWN cache, where RAM has NO EFFECT.

Nextime, read my post all the way through Lord K, instead of making me repeat myself. Face it, you were wrong. Maybe next week, you will be right.
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Old 02-19-2005, 01:44 PM   #85
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Well that's not L1 Cache information is it? That's L1 Cache on an AMD Processor information.

The L1 Cache eventually Caches RAM Data And whether its in the Processor or not, its still Randomly Accessed - and a Form of Memory.

What you're saying is that the Synax of the answer was misinterpreted, not that we were wrong
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Old 02-19-2005, 01:53 PM   #86
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Default Re: AMD ZEN'S HYPERQUIZ! (Week3) VOTING OVER!!!!

Ram Has Nothing To Do With The L1 Cache!!!!!!!! Nothing!!! It Is Totally Internal To The Processor!! If Ram Had Anything To Do With The L1, You Could Kiss Your Pc Goodbye!!!
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Old 02-19-2005, 01:55 PM   #87
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Default Re: AMD ZEN'S HYPERQUIZ! (Week3) VOTING OVER!!!!

YeaHG, Who was right, Me that right now i am
3 for 3 heheheh

hay, w is lk only a guru, was he not just a moD???
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Old 02-19-2005, 01:57 PM   #88
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Default Re: AMD ZEN'S HYPERQUIZ! (Week3) VOTING OVER!!!!

You were actually wrong Necro, it was the answer that only 9 people got, the one below your choice...... SRY BUD. It was a trick question.
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Old 02-19-2005, 02:11 PM   #89
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Default Re: AMD ZEN'S HYPERQUIZ! (Week3) VOTING OVER!!!!

Ok thenm I am 2 for 3 dqamnit, Well Amd ZEn you have cought me in a lie, I am ashamed.

:sound of knife coming out of its sheath, sound of Scrotum hiting the floor: ouch. no worrys they grow back.
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Old 02-19-2005, 02:40 PM   #90
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Default Re: AMD ZEN'S HYPERQUIZ! (Week3) VOTING OVER!!!!

Lmao!!!
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