tCAS
The number of clock cycles needed to access a certain column of Data in SDRAM. CAS Latency, or simply CAS, is known as Column Address Strobe Latency, sometimes referred to as tCL.
tRCD (RAS to CAS Delay)
The number of Clock cycles needed between a Row Address Strobe (RAS) and a CAS. It is the time required between the computer defining the row and column of the given memory block and the actual read or write to that location. Stands for Row address to Column address Delay.
tRP (RAS Precharge)
The number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. Stands for Row precharge time.
tRAS
The minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. Known as Active to Precharge Delay.
