Intel's new CPU

[TRDCorolla1]

Have you guys wondered what the next generation Intel CPU would be like? They are actually going backwards with their new architecture. It will use a 14-stage pipeline, compared to the Pentium 4's 21-stage pipeline and to Prescott's 30-stage pipeline. With that in mind, it's looking more like Intel's 6th generation CPU, the Pentium III, than Intel's 7th generation CPUs. How funny is that? Despite that, it will still be able to send more instructions which obviously increases performance.

On the cache side, it will use a shared L2 cache for all the CPU cores, just like Yonah, the dual-core Pentium M CPU manufactured in the new 65-nm process that will be released in the beginning of next year. This was made in order to decrease the cache-miss rate, i.e. decrease the number of times that the CPU run out of cache and needs to go to the slow RAM memory to grab data.

With a shared L2 cache between all CPU cores, the CPU can give more or less L2 cache for each core depending on the demand. In a dual core CPU with separated L2 caches, if one core runs out of cache, it must go and get data directly on the RAM memory, even if the L2 cache from the other core has plenty of space available. On the shared model, if the CPU has 2 MB total L2 cache, for example, one core may be using 1.5 MB and the other 0.5 MB of it, which decreases the number of times the CPU needs to grab data directly on RAM memory, increasing performance.

Intel is also promising that the L1 memory caches from each core will be able to directly communicate to each other and also a higher bandwidth between the CPU core and the L2 memory cache.

Another thing new on this architecture will be a new multimedia instruction set (perhape SSE4?), the fifth multimedia instruction set since MMX was released back in 1996.

All CPUs will incorporate the 64-bit addressing extension, EM64T.

The difference between Merom, for mobile market, Conroe, for desktops, and Woodcrest, for servers, will be basically the L2 memory cache size, the TLB (Translation Look-aside Buffer) size and the amount of RAM memory the CPU can address. TLB is a table used by the virtual memory system (a.k.a. swap file) that lists the physical address page number associated with each virtual address page number.

We may just see Intel stepping up big next year.

 

[catalyst1]

Well, aren't Intel's mobile chips based on the P3 architecture? Maybe they realize that they had some good stuff with the P3s and are running with it. Perhaps they are beginning to take after AMD with their "slower clock speed but harder working processor" philosophy. That seems to be the case with the mobiles anyway.

 

[TRDCorolla1]

Yup. Intel's Prescott is just way too inefficient. Pipeline is like a list of all stages a given instruction must go through in order to be fully executed. On 6th generation Intel processors, like Pentium III, their pipeline had somewhere like 11 stages, I believe. Pentium 4 has 20 stages! So, on a Pentium 4 processor a given instruction takes much longer to be executed then on a Pentium III!! For example, if you take the 90 nm Pentium 4 generation processor known as Prescott, the case is even worse because they use a 31-stage pipeline!

This was done in order to increase the processor clock rate. By having more pipeline stages, each individual stage can be constructed using fewer transistors. With fewer transistors, it is easier to achieve higher clock rates. In fact, Pentium 4 is only faster than Pentium III because it works at a higher clock rate. Under the same clock rate, a Pentium III CPU would be faster than a Pentium 4 because of the size of the pipeline. How's that for knowledge?

Because of that, Intel has already announced that their 8th generation processors which will use the Pentium M architecture, based on Intel's 6th generation Pentium III and not on Netburst (Pentium 4) architecture so Spank Fusion, you are correct.

 

[draconum]

Awsome stuff, seems like intel is starting to actually get smart, though I dought I'll be using them anytime soon unless I buy a mac with one. other then that I'll stick with my AMD processors thank you



Chris

 

[alvino]

Yes, I talked about the Conroe core before. What I'm most excited about, however, is the Yonah and Merom cores...oh baby. If Intel pulls that off, AMD is gonna have a hard time getting them in the mobile market (which is the key to Intel's defeat).

 

[TRDCorolla1]

Not just the mobile CPU, but desktop units as well. The difference between Merom, for mobile market, Conroe, for desktops, and Woodcrest, for servers, will be basically the L2 memory cache size, the TLB (Translation Look-aside Buffer) size and the amount of RAM the CPU can address.

Speaking of AMD, there are rumors of DDR3 development but cost is a huge factor. Socket M2 may as well use the 65nm process, but that's going to be a huge transition point.

During a press conference for financial analysts, AMD gave the broad outlines of the 2006 and 2007 roadmaps as seen above.

Three main innovations will take place in 2006 additionally to the usual frequency increases. First, the DDR2 support then the Presidio and Pacifica technologies.

Presidio technology is the same as LaGrande for Intel. This function increases the security level, but could have unpleasant consequences as it's based on the Palladium technology, already the subject of many articles about possible misuses.

Pacifica is the equivalent of the Virtual Technology (VT) for Intel also known as VanderPool. Pacifica permits the dissociation of the OS from the hardware and allows the operation of several OSs on a single computer.

 

[alvino]

That too, but the majority of Intel's profits is from the Pentium M and it's Centrino Technology. AMD has to try to be superior in that category in order to really hurt Intel.

 

[TRDCorolla1]

Those picts above pretty much says it all for what AMD plans to do. DDR3 and DDR4?!?!? Coming soon...

"Biggest changes will take place in 2007. For servers, the release of multi core processors (4 cores apparently) has been brought up with the possibility to include 32 or more processors. These processors will require a cache L3 additionally to a “X GHz” HyperTransport bus, which will be at least two times faster than the current 1 “GHz”.

Desktop processors won't be left out in 2007 with the release of new cores. AMD hasn't specified whether if they will be dual or quadri cores. These cores will feature bigger cache, a new HT bus and will support DDR3 memory. If AMD plans to launch dual core processors for laptops in 2006, in 2007 they will feature bigger but shared cache and will support DDR3 memory. According to AMD's plan, DDR2 memory will be quickly replaced by the DRR3. For long term, AMD mentioned FPU extensions for the AMD64, a new architecture, coprocessors integrated to processor, HyperTransport 4, DDR4 … but didn't give any details. It is nice to let us imagine what will happen, but we would have appreciated a couple of information."

Maybe I should've broken this up into a Intel and AMD thread instead.

 

[catalyst1]

Intel is working on quad core processors as well, but what really caught my eye on those AMD roadmaps was the sub-10W spec for blade PCs and thin clients in 2006. That's crazy! Definitely a good move. The less cooling necessary, the better. Especially only 10W!!!!

 

[TRDCorolla1]

I know huh? How are they even planning to do that? It will be very interesting to see when the time comes near for their release. Here we are in 2005 and it's funny to see what may happen in 2007. DDR3, increase and enhance HT, second generation PCI-e, etc...that just clears all my list of new hardware to buy. Those ideas make today's technoloy look sooo obsolete.